Area-Time Efficient Hardware Implementation of Elliptic Curve Cryptosystem

The strength of ECC lies in the hardness of elliptic curve discrete logarithm problem (ECDLP) and the hight level security with significantly smaller keys. Thus, using smaller key sizes is a gain in term of speed, power, bandwidth, and storage. Point multiplication is the most common operation in ECC and the most used method to compute it is Montgomery Algorithm. This paper describes an area-efficient hardware implementation of Elliptic Curve Cryptography (ECC) over GF (2). We used the Montgomery modular multiplication method for low cost implementation. Then, to accelerate the elliptic curve point multiplication, we firstly adopted projective coordinates, and then we reduced the number of multiplication block used, so we have a gain at area occupation and execution time. We detailed our optimized hardware architecture and we prove that it outperform existing ones regarding area, power, and energy consumption. Our hardware implementation, on a Xilinx virtex 5 ML 50 FPGA, used only 9670 Slices achieving maximum frequency of 221 MHz, it computed scalar multiplication in only 2.58 μs. FPGA implementations represent generally the first step to obtain faster ASIC implementations.Further, we implemented our design on an ASIC CMOS 45 nm technology, it uses 0.121 mm of area cell, it runs at a frequency of 990 MHz and consumes 39(mW).